1. Field of Invention
This invention relates to improvements in electrical circuits, and more particularly to circuits and methods for fast response current limiting.
2. Relevant Background
A prior-art two-stage amplifier 10 is shown in FIG. 1 for driving an output circuit 12, having a load, RL, 18 and an nMOS output power transistor, MPOWER, 20. The circuit 10 may be, for example, an integrated circuit, with the circuit 12 provided either as a part thereof, or externally connected thereto.
The amplifier 10 has two stages 14 and 16. The first amplifier stage 14 has two PNP transistors Q1, 22, and Q2, 24, which have an emitter area ratio of 1X/NX. The transistors 22 and 24 have respective associated nMOS current mirror transistors M2, 26, and M3, 28. The transistors 26 and 28 mirror the current in nMOS transistor M1, 30, which is connected to current source 32 that provides a current IB thereto. If the nMOS transistors 26 and 28 are designed to conduct equal currents, an input-referred voltage offset VPTAT will occur between the PNP transistors 22 and 24 due to their size differences and resulting different current densities therein. Assuming transistors 22 and 24 operate in low-level injection, the magnitude of the voltage offset equalsVPTAT=VT ln(N)  [1]
where VT is the thermal voltage (VT=kT/q, where k is Boltzmann's constant, T is the absolute temperature, and q is the charge on the electron), and where N is the emitter ratio as described above).
Since the circuit 10 is preferably fabricated as a single integrated circuit, the resistor RAl across which the input voltage is developed is preferably constructed of aluminum metallization, which has a temperature coefficient of about 3000 ppm/° C. The temperature coefficient of the resistor then matches (at least approximately) the temperature coefficient of the voltage VPTAT. Therefore the current limit I-lim generated by circuit 10 is largely independent of temperature. This current limit equals
                              I          lim                =                                            V              T                        ⁢                          ln              ⁡                              (                N                )                                                          R            AI                                              [        2        ]            
In response to the input voltage across RAl, the first amplifier stage 14 generates a current IX that is sunk into MOS transistor M4 of the second amplifier stage 16. The magnitude of current IX equals:
                              I          X                =                              I            S                    ⁢                                          ⁢                      exp            ⁡                          (                                                                    V                    IN                                    -                                      V                    PTAT                                                                    V                  T                                            )                                                          [        3        ]                            where Is is the saturation current of Q1, and VIN equals the differential voltage appearing across resistor RAl. The current IX is referred to herein as a “control current”.        
The second amplifier stage 16 includes a first nMOS transistor M4, 46, connected to receive the control current IX, and a second nMOS transistor M5, 38, connected to a current source 40, which provides a current ICP.
The first transistor 46 amplifies the control current IX to develop a control voltage, which is applied to the gate of the second transistor 38. The second transistor 38 generates an output current, which, in the embodiment illustrated controls the voltage at the gate of the output power transistor 20.
The frequency response of the amplifier of circuit 10 has two important poles. The first is an internal pole caused by capacitance CX acting against the resistance at node 36. The second is a gate pole caused by the capacitance Cg acting against the resistance at node 43. In order to maintain adequate stability, the gain of the circuit must drop below unity before the phase margin drops below about 30°. This requires either that one of the poles be pushed back to a very low frequency (dominant-pole compensation) or that the gain of the circuit be artificially reduced.
Dominant-pole compensation is greatly complicated by the movement of the gate pole due to variations in effective gate capacitance Cg with load resistance RL. If RL is shorted, then Cg includes a large contribution from the gate-to-source capacitance Cgs of the output power transistor 20. Larger values of RL decrease the contribution of Cgs to Cg. Dominant-pole compensation can still be achieved either by adding a large capacitance to node 43, or by connecting a Miller capacitance around transistor 38, but both solutions have the undesirable property of slowing the transient response of the amplifier.
The addition of transistor 46 greatly reduces the resistance at node 36. This has two beneficial effects. First, it reduces the loop gain, and second, it pushes the internal pole out to a higher frequency, effectively forcing the gate pole to become the dominant pole of the system. The addition of transistor 46 therefore compensates the amplifier without requiring the addition of any extraneous capacitance. The offset introduced by current IX can be compensated by drawing an equal current from node 45.
The circuit of FIG. 1 responds relatively rapidly to large input signals, such as those generated by hot-shorting the load RL. The current available to slew the gate capacitance is the current in transistor 38, which equals
                              I          M5                =                                                            (                                  W                  /                  L                                )                            5                                                      (                                  W                  /                  L                                )                            4                                ⁢                      I            X                                              [        4        ]            
where (W/L)5 and (W/L)4 are respectively the width to length ratios of the nMOS transistors M5, 38, and M4, 46. As equation [3] indicates, this current is exponentially dependent upon the magnitude of the input voltage. This equation does not consider the terminal resistances of transistors 22 and 24, nor their finite betas. These factors will ultimately limit the current IX, and through it, the response time of circuit 10.